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Development of a new CMOS clocking technology with ultra high-accuracy and mitigated aging. The clock reference was targeted for 10 ppm accuracy and 5 ppm of aging. Several state of the art systems and circuits have been developed and patented.
Circuit design for peripheral and analog interface circuits for MRAM chip in 90 nm CMOS technology. Designed blocks included Class AB buffers, ring oscillators and DDR/DLL interface.
System and circuit design of an LTE mobile phone low-IF receiver front-end in 65 nm CMOS technology. Designed blocks included a gain/band programmable LNA, an image reject mixer, an IF polyphase BP filter and a PGA.
Design of power circuits such as voltage regulators, motor drivers and dc-dc converters for automotive applications in CMOS 180 nm technology.
System and circtuit design of a fast CMOS ADC and DAC in 65 nm technology. Sampling rate 2 Gbps, ENOB -6.5 bits for DAC and 6.0 bit for ADC.
Design of LDO in CMOS 90 nm technology.Regulated voltage 1.2 V, current 400 mA. Low dropout voltage of 190 mV. Low output noise of 0.2 µV.
System and circuit design for an 8 GHz VCO in an advanced submicron CMOS process. Main challenge was delivering a stringent phase-noise spec, while complying with a very low critical breakdown voltage.
System design of a zero-IF DVB-H tuner. Balance of system level IIP3, IIP2 and noise performance. Designing the individual block specs. Review of the block performance with respect to the system spec. Mentoring the block designers in order to improve the overall performance.
System and circuit design for a Si-Ge BiCMOS AGC-less IF-strip consisting of gm-C filters and gain blocks for a zero-IF data receiver.
Feasibility study for system and circuit design of a CMOS universal analog/DTV/cable TV tuner. Both low-IF and zero-IF architectures have been evaluated and designed. Fixed-video (ATSC, DVB-T, ISDB-T, NTSC, PAL), cable (DVB-C, DOCSIS) and mobile-video (DVB-H, ISDB-T) tuners have been initially designed and tested. Six patents have been filled and all have been granted.
Circuit design and test procedure for RF wafer-probe test structures for all fundamental block of a 2.4/5.7 GHz 802.11 transceiver in Si-Ge BiCMOS technology.The blocks included LNA, down-mixer, VCO, divider, up-mixer and driver amplifier. BiCMOS and straight CMOS block versions have been designed and its performance evaluated and compared.
System and circuit design for BiCMOS continuous-time real and complex gm-C IF- filters for GPS low-IF receiver.
System and circuit design for a CMOS W-CDMA IF-channel consisting of receive and transmit parts.Implementation of VGAs, mixers, phase shifters, on-chip VCO and PLL. Two patents applied for and granted jointly with the customer.
System and circuit design for a bipolar GPS receiver consisting of LNA, mixer, VGAs, AGC and PLL.
Feasibility study for the design of a CMOS 900 MHz ISM-band transmitter with on-chip VCO and power amplifier.
Si-Ge BiCMOS implementation for a PCS/AMPS handset receiver RF front-end including LNAs, mixers, switches and bias blocks.
Feasibility study for system and circuit design for a CDMA receiver CMOS RF front-end consisting of LNA, mixers and IF amplifier.