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Digital ASICs

A list of typical steps performed to design a Digital ASIC include:

  • Architecture specification for top and module levels

-          define interface signals based on functional requirements

-          system level register definition, including control/status registers for efficient system and software interaction

-          specification of clock, reset and external peripheral device schemes, as well as internal state machine and datapath structure for optimized hardware implementation

-          specification of simulation, verification and test plans

        RTL hand-off service

-          generate RTL model in compliance to the Architecture Specification in Verilog and/or VHDL description

-          create top-level and module-level test benches, test cases and stimuli for functional verification of the RTL model

        Logic Synthesis from RTL to gate-level netlist

-          generate module level and top-level design constraints to address various implementation concerns in speed, area, driving power, etc.

-          optimize synthesis flow and provide push-button solution for future re-synthesis routine

-          hand-off verified gate level netlist to meet timing requirements

-          provide formal verification as proof of netlist consistency with RTL model

        Design for testability

-          internal scan chain insertion based on customer testability requirements and test plan

-          build-in self test (BIST) circuitry design for memory modules

-          chip level boundary scan chain insertion in compliance with JTAG standard

-          test pattern generation

        Post-layout verification and timing-closure

-          gate-level simulation with post-layout delay information

-          timing closure with multiple operation modes to fix timing violations

-          engineering change order (ECO) process to fix gate-level errors and deliver final tape-out file in GDS format


Digital ASIC Design Flow


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